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The Intel 8031 (or later 8051) is a very common architecture that is used in many microcontrollers from several manufacturers. There are many optimizing 8051 compilers available. Some of them are free, while professional development packages can cost a significant amount of money. Anyway, even in the world of 32-bit microcontrollers the 8051 family is still popular.
The universal 8031 architecture sports a Harvard architecture, which contains two separate buses for both program and data. So, it has two distinctive memory spaces of 64K X 8 size for both program and data. It is based on an 8 bit central processing unit with an 8 bit Accumulator and another 8 bit B register as main processing blocks. Other portions of the architecture include few 8 bit and 16 bit registers and 8 bit memory locations.
Each 8031 device has some amount of data RAM built in the device for internal processing. This area is used for stack operations and temporary storage of data. This base architecture is supported with onchip peripheral functions like I/O ports, timers/counters, versatile serial communication port. So it is clear that this 8031 architecture was designed to cater many real time embedded needs. The following list gives the features of the 8031 architecture:
- Optimized 8 bit CPU for control applications.
- Extensive Boolean processing capabilities.
- 64K Program Memory address space.
- 64K Data Memory address space.
- 128 bytes of onchip Data Memory.
- 32 Bi-directional and individually addressable I/O lines.
- Two 16 bit timer/counters.
- Full Duplex UART.
- 6-source / 5-vector interrupt structure with priority levels.
- Onchip clock oscillator.
Now you may be wondering about the non mentioning of memory space meant for the program storage, the most important part of any embedded controller. Originally this 8031 architecture was introduced with onchip, ‘one time programmable’ version of Program Memory of size 4K X 8. Intel delivered all these microcontrollers (8051) with user’s program fused inside the device. The memory portion was mapped at the lower end of the Program Memory area. But, after getting devices, customers couldn’t change any thing in their program code, which was already made available inside during device fabrication.
So, very soon Intel introduced the 8031 devices (8751) with re-programmable type of Program Memory using built-in EPROM of size 4K X 8. Like a regular EPROM, this memory can be re-programmed many times. Later on Intel started manufacturing these 8031 devices without any onchip Program Memory. Now I go ahead giving more information on the important functional blocks of the 8031.
Central Processing Unit
The CPU is the brain of the microcontrollers reading user’s programs and executing the expected task as per instructions stored there in. Its primary elements are an 8 bit Arithmetic Logic Unit (ALU), Accumulator (Acc), few more 8 bit registers, B register, Stack Pointer (SP), Program Status Word (PSW) and 16 bit registers, Program Counter (PC) and Data Pointer Register (DPTR). The ALU (Acc) performs arithmetic and logic functions on 8 bit input variables. Arithmetic operations include basic addition, subtraction, multiplication and division. Logical operations are AND, OR, xclusive OR as well as rotate, clear, complement and etc. Apart from all the above, ALU is responsible in conditional branching decisions, and provides a temporary place in data transfer operations within the device.
B register is mainly used in multiply and divide operations. During execution, B register either keeps one of the two inputs and then retains a portion of the result. For other instructions, it can be used as another general purpose register. Program Status Word keeps the current status of the ALU in different bits.
Stack Pointer (SP) is an 8 bit register. This pointer keeps track of memory space where the important register information are stored when the program flow gets into executing a subroutine. The stack portion may be placed in any where in the onchip RAM. But normally SP is initialized to 07H after a device reset and grows up from the location 08H. The Stack Pointer is automatically incremented or decremented for all PUSH or POP instructions and for all subroutine calls and returns. Program Counter (PC) is the 16 bit register giving address of next instruction to be executed during program execution and it always points to the Program Memory space.
Data Pointer (DPTR) is another 16 bit addressing register that can be used to fetch any 8 bit data from the data memory space. When it is not being used for this purpose, it can be used as two eight bit registers.
Input / Output Ports
The 8031’s I/O port structure is extremely versatile and flexible. The device has 32 I/O pins configured as four eight bit parallel ports (P0, P1, P2 and P3). Each pin can be used as an input or as an output under the software control. These I/O pins can be accessed directly by memory instructions during program execution to get required flexibility. These port lines can be operated in different modes and all the pins can be made to do many different tasks apart from their regular I/O function executions. Instructions, which access external memory, use port P0 as a multiplexed address/data bus. At the beginning of an external memory cycle, low order 8 bits of the address bus are output on P0. The same pins transfer data byte at the later stage of the instruction execution.
Also, any instruction that accesses external Program Memory will output the higher order byte on P2 during read cycle. Remaining ports, P1 and P3 are available for standard I/O functions. But all the 8 lines of P3 support special functions: Two external interrupt lines, two counter inputs, serial port’s two data lines and two timing control strobe lines are designed to use P3 port lines. When you don’t use these special functions, you can use corresponding port lines as a standard I/O. Even within a single port, I/O operations may be combined in many ways. Different pins can be configured as input or outputs independent of each other or the same pin can be used as an input or as output at different times. You can comfortably combine I/O operations and special operations for Port 3 lines.
Timers / Counters
8031 has two 16 bit Timers/Counters capable of working in different modes. Each consists of a ‘High’ byte and a ‘Low’ byte which can be accessed under software. There is a mode control register and a control register to configure these timers/counters in number of ways. These timers can be used to measure time intervals, determine pulse widths or initiate events with one microsecond resolution upto a maximum of 65 millisecond (corresponding to 65, 536 counts). Use software to get longer delays. Working as counter, they can accumulate occurrences of external events (from DC to 500KHz) with 16 bit precision.
Serial Port
Each 8031 microcomputer contains a high speed full duplex (means you can simultaneously use the same port for both transmitting and receiving purposes) serial port which is software configurable in 4 basic modes: 8 bit UART; 9 bit UART; Interprocessor Communications link or as shift register I/O expander.
For the standard serial communication facility, 8031 can be programmed for UART operations and can be connected with regular personal computers, teletype writers, modem at data rates between 122 bauds and 31 kilobauds. Getting this facility is made very simple using simple routines with option to select even or odd parity. You can also establish a kind of Interprocessor communication facility among many microcomputers in a distributed environment with automatic recognition of address/data. Apart from all above, you can also get super fast I/O lines using low cost simple TTL or CMOS shift registers.
There are many interesting 8051 projects that use one of the microcontroller from this family. It is amazing that this 8-bit family is still popular today.
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Tags: 8051
Posted in Hardware · June 9th, 2010 · Comments (0)
A network protocol is a standard that allows computers to communicate with each other across some form of link. The protocol needs to define how the computers interact with the network and then how they find the device they want to communicate with. A good protocol should also define how to handle damaged transmissions. IPX, TCP/IP, DECnet, AppleTalk, LAT, X.25, Netware/IPX, and NetBEUI are all well-known examples of network protocols.
We start by looking at how the computer gets on to the network in the first place. The precursor to Ethernet-ALOHA-had the simplest possible scheme for gaining access to a shared medium. When a terminal had something to send, it simply sent it, regardless of what anyone else was doing. If another computer tried to send at the same time, the two messages would collide, both would be corrupted, and everyone would have to back off for a while before starting again. It was only when you received an acknowledgement to your message that you could be sure that it had arrived safely and there had been no collision. Of course, you might have had to wait for the acknowledgment as it, too, could have suffered a collision. This was not an efficient way to control access, so a more sophisticated mechanism was sought.
Enter slotted ALOHA. Now transmissions were constrained to occur in frames, rather than at any time. This meant that collisions only occurred when two terminals chose to transmit in the same frame (rather than when there was any overlap at all between the two transmissions). This simple modification led to a significant improvement in throughput, allowing up to 35% of the channel capacity to be used, compared with a previous peak utilization of less than 20%.
Ethernet built on the lessons of ALOHA by enforcing the following regime:
Terminals always listen before they send.
They do not send when someone else is doing so.
When they do send, they limit the amount of data that is transmitted.
If they find themselves sending at the same time as someone else, they back off.
These are much the same set of rules that govern a (polite) telephone conference. The main addition to the ALOHA practice is to listen before sending. If the medium is free, the terminal can transmit immediately. If it is busy, it backs off for a random time before trying again.
Collisions still occur, of course, as it takes a finite time for frames to travel from one point of connection to another. Therefore, two terminals may start to send, both believing the medium to be free, only to find out that someone else has already started to send at the same time.
The fundamental physics of transmission speed have an impact on the range of frame sizes that are specified for use on an Ethernet. If two stations are at opposite ends of the network they need to know when the other one is transmitting. If the frame length is too short, then this is compromised. The listening station is unaware that the medium is busy, so it would feel free to send. A collision would then happen close by this station. Meanwhile, the station that had already sent the frame would be blissfully ignorant of what was going on at the other end of the network and would have to wait to find out if there had been a collision.
In order to remove the indeterminacy caused by frames in transit, a minimum frame size is needed. This is equal to twice the propagation time from one end of the network to the other. With multiple sections joined by repeaters, there can be up to 2.5 km between the two end stations. Hence, with signals traveling at a speed of about 2 × 108 m/sec, the “there and back” propagation time is just over 50 ms. At a bit rate of 10 Mbps, this equates to a minimum frame size of 64 bytes.
The mechanism for controlling access described above is known as collision sense multiple access/collision detect (CSMA/CD). It has proved a simple yet effective way of admitting traffic on to the network. Adjusting the back-off time after a collision and the maximum frame size that can be sent both help to ensure fair access and increase the achievable throughput of data across the network. In practice, CSMA/CD Ethernets could cope perfectly well with traffic loads that previously used up to 70% of available bandwidth.
Now that we have a solution to the main problem of accessing shared media, the issue of getting the right connection remains. This is where the address resolution protocol (ARP) for IP comes in handy.
All stations attached to an Ethernet have a physical address-a 48-bit (or 6-byte) identifier known as the hardware or media access control (MAC) address. When user A wants to communicate with user B at another station, it must know both the MAC address and the destination station’s higher level protocol address (i.e., its IP address). To obtain station B’s IP address, user A’s computer composes a packet known as an ARP request, encapsulates this within an Ethernet frame, and “broadcasts” this to all stations on the Ethernet.
Typically, the ARP request contains the destination IP address of the intended host, since this is the most commonly recognized form of identification these days. However, ARP variants have been developed for nearly every protocol operated over Ethernet, including Novell/Netware, AppleTalk, and DECnet.
The hardware location of the addressee is not known to start with, so the hardware address field in the broadcast message is set to zero. The frame containing the ARP request is broadcast to all devices connected to the Ethernet by setting the destination Ethernet address to all ones (FF FF FF FF FF FF). All stations on an Ethernet must listen for and process frames having this broadcast address as the destination MAC address.
When the broadcast frame is received, the station (B) whose upper level address (i.e., its IP address) matches the address encoded in the ARP request is the only one that responds to the broadcasting station. It returns an ARP reply message containing its hardware (MAC) address, which is inserted in the field that was previously set to zero.
When computer A receives and processes the ARP response message, it will maintain association of the logical IP address of the intended recipient with its physical MAC address in what is called an ARP cache. Once this step is complete, IP packets can be sent between the two without further concern; a logical path now exists between the sender and receiver.
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Tags: ethernet
Posted in Hardware · June 7th, 2010 · Comments (0)